This section describes the main features of the TMS320VC5410 digital signal processor (DSP), lists the pin assignments, and describes the function of each pin. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging.
Description
The TMS320VC5410 fixed-point, digital signal processor (DSP) (hereafter referred to as the 5410 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.
Features
• Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
• 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
• 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
• Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
• Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
• Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
• Data Bus With a Bus Holder Feature
• Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space
• 64K x 16-Bit On-Chip RAM Composed of:
-- Four Blocks of 2K × 16-Bit On-Chip Dual-Access Program/Data RAM