The TMS320C5535AZHH10 is a Digital Signal Processor designed for low-power applications. The fixed-point DSP is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.
One or two instructions executed per cycle
Two arithmetic and logic units (ALUs)
Three internal data or operand read buses and two write buses
Software-compatible with C55x Devices
Tightly coupled FFT hardware accelerator
Two embedded multimedia card (eMMC) or secure digital (SD) interfaces
