The ST10F280 is a new derivative of the ST Microelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 20 million instructions per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides on-chip high-speed single voltage FLASH memory, on-chip high-speed RAM, and clock generation via PLL.
■ HIGH PERFORMANCE CPU WITH DSP FUNCTIONS
\- 16-BIT CPU WITH 4-STAGE PIPELINE.
\- 50ns INSTRUCTION CYCLE TIME AT 40MHz CPU CLOCK.
\- MULTIPLY/ACCUMULATE UNIT (MAC) 16 X 16-BIT MULTIPLICATION, 40-BIT ACCUMULATOR
\- REPEAT UNIT.
\- ENHANCED BOOLEAN BIT MANIPULATION FACILITIES.
\- ADDITIONAL INSTRUCTIONS TO SUPPORT HLL AND OPERATING SYSTEMS.
\- SINGLE-CYCLE CONTEXT SWITCHING SUPPORT.
■ MEMORY ORGANIZATION
\- 512K BYTE ON-CHIP FLASH MEMORY SINGLE VOLTAGE WITH ERASE/PROGRAM CONTROLLER.
\- 100K ERASING/PROGRAMMING CYCLES.
\- 20 YEAR DATA RETENTION TIME
\- UP TO 16M BYTE LINEAR ADDRESS SPACE FOR CODE AND DATA (5M BYTE WITH CAN).
\- 2K BYTE ON-CHIP INTERNAL RAM (IRAM).
\- 16K BYTE EXTENSION RAM (XRAM).
■ FAST AND FLEXIBLE BUS
\- PROGRAMMABLE EXTERNAL BUS CHARACTERIS TICS FOR DIFFERENT ADDRESS RANGES.
\- 8-BIT OR 16-BIT EXTERNAL DATA BUS.
\- MULTIPLEXED OR DEMULTIPLEXED EXTERNAL ADDRESS/DATA BUSES.
\- FIVE PROGRAMMABLE CHIP-SELECT SIGNALS.
\- HOLD-ACKNOWLEDGE BUS ARBITRATION SUPPORT.
■ INTERRUPT
\- 8-CHANNEL PERIPHERAL EVENT CONTROLLER FOR SINGLE CYCLE, INTERRUPT DRIVEN DATA TRANSFER.
\- 16-PRIORITY-LEVEL INTERRUPT SYSTEM WITH 56 SOURCES, SAMPLE-RATE DOWN TO 25ns.
■ TWO MULTI-FUNCTIONAL GENERAL PURPOSE TIMER UNITS WITH 5 TIMERS.
■ TWO 16-CHANNEL CAPTURE/COMPARE UNITS
■ A/D CONVERTER
\- 2X16-CHANNEL 10-BIT.
\- 4.85µS CONVERSION TIME
\- ONE TIMER FOR ADC CHANNEL INJECTION
■ 8-CHANNEL PWM UNIT
■ SERIAL CHANNELS
\- SYNCHRONOUS/ASYNC SERIAL CHANNEL
\- HIGH-SPEED SYNCHRONOUS CHANNEL.
■ FAIL-SAFE PROTECTION
\- PROGRAMMABLE WATCHDOG TIMER.
\- OSCILLATOR WATCHDOG.
■ TWO CAN 2.0b INTERFACES OPERATING ON ONE OR TWO CAN BUSSES (30 OR 2X15 MESSAGE OBJECTS)
■ ON-CHIP BOOTSTRAP LOADER
■ CLOCK GENERATION
\- ON-CHIP PLL.
\- DIRECT OR PRESCALED CLOCK INPUT.
■ UP TO 143 GENERAL PURPOSE I/O LINES
\- INDIVIDUALLY PROGRAMMABLE AS INPUT, OUT PUT OR SPECIAL FUNCTION.
\- PROGRAMMABLE THRESHOLD (HYSTERESIS).
■ IDLE AND POWER DOWN MODES
■ MAXIMUM CPU FREQUENCY 40MHz
■ PACKAGE PBGA 208 BALLS (23mm x 23mm x 1.96 mm - PITCH 1.27mm).
■ SINGLE VOLTAGE SUPPLY: 5V ±10% (EMBEDDED REGULATOR FOR 3.3 V CORE SUPPLY).
