The SN74LVC1G08MDCKREP is an enhanced product single 2-input positive-AND Gate and performs the Boolean function Y = A • B or Y = (A\ + B\\)\ in positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
±24mA Output drive at 3.3V
10µA Maximum ICC low power consumption
Maximum tpd of 3.6ns at 3.3V
Inputs accept voltages to 5.5V
Ioff supports partial-power-down mode operation
Supports 5V VCC operation
Controlled baseline - one assembly/test site, one fabrication site
Enhanced diminishing manufacturing sources (DMS) support
Enhanced product-change notification
Qualification pedigree
Latch-up performance exceeds 100mA per JESD 78, Class II