The SN65LVDM176D is a half-duplex LVDM Transceiver uses low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbit/s. The circuits are similar to TIA/EIA-644 standard compliant devices (SN65LVDS) counterparts except that the output current of the drivers is doubled. This modification provides a minimum differential output voltage magnitude of 247mV into a 50R load and allows double-terminated lines and half-duplex operation. The receivers detect a voltage difference of less than 50mV with up to 1V of ground potential difference between a transmitter and receiver. The intended application of this device and signaling technique is for half-duplex or multiplex baseband data transmission over controlled impedance media of approximately 100R characteristic impedance. The transmission media may be printed-circuit board traces, backplanes or cables.
Designed for signalling rates of 400 Mbit/s
ESD protection exceeds 15kV on bus pins
Low-voltage differential signalling
Valid output with as little as 50mV input voltage difference
1.7ns Driver, 3.7ns receiver propagation delay times
LVTTL levels are 5V tolerant
Bus pins are high impedance when disabled or with VCC less than 1.5V