The NB3N502DG is a Clock Multiplier Device that generates a low jitter, TTL/CMOS level output clock which is a precise multiple of the external input reference clock signal source. The device is used for the crystal oscillators commonly used in electronic systems. It accepts a standard fundamental mode crystal or an external reference clock signal. Phase-locked-loop (PLL) design technique is used to produce an output clock up to 190MHz with a 50% duty cycle. This can be programmed via two select inputs to provide an output clock (CLKOUT) at one of six different multiples of the input frequency source and at the same time output the input aligned reference clock signal (REF).
