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ispMACH
4000V/B/C/Z Family
3.3V/2.5V/1.8V In-System Programmable
SuperFAST
High Density PLDs
May 2009 Data Sheet DS1020
®
TM
© 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Features
High Performance
•f
MAX
= 400MHz maximum operating frequency
•t
PD
= 2.5ns propagation delay
• Up to four global clock pins with programmable
clock polarity control
• Up to 80 PTs per output
Ease of Design
• Enhanced macrocells with individual clock,
reset, preset and clock enable controls
• Up to four global OE controls
• Individual local OE control per I/O pin
• Excellent First-Time-Fit
TM
and refit
• Fast path, SpeedLocking
TM
Path, and wide-PT
path
• Wide input gating (36 input logic blocks) for fast
counters, state machines and address decoders
Zero Power (ispMACH 4000Z) and Low
Power (ispMACH 4000V/B/C)
• Typical static current 10µA (4032Z)
• Typical static current 1.3mA (4000C)
• 1.8V core low dynamic power
• ispMACH 4000Z operational down to 1.6V V
CC
Broad Device Offering
• Multiple temperature range support
– Commercial: 0 to 90°C junction (T
j
)
– Industrial: -40 to 105°C junction (T
j
)
– Extended: -40 to 130°C junction (T
j
)
• For AEC-Q100 compliant devices, refer to
LA-ispMACH 4000V/Z Automotive Data Sheet
Easy System Integration
• Superior solution for power sensitive consumer
applications
• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
• Operation with 3.3V (4000V), 2.5V (4000B) or
1.8V (4000C/Z) supplies
• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI
interfaces
• Hot-socketing
• Open-drain capability
• Input pull-up, pull-down or bus-keeper
• Programmable output slew rate
• 3.3V PCI compatible
• IEEE 1149.1 boundary scan testable
• 3.3V/2.5V/1.8V In-System Programmable
(ISP™) using IEEE 1532 compliant interface
• I/O pins with fast setup path
• Lead-free package options
Table 1. ispMACH 4000V/B/C Family Selection Guide
ispMACH
4032V/B/C
ispMACH
4064V/B/C
ispMACH
4128V/B/C
ispMACH
4256V/B/C
ispMACH
4384V/B/C
ispMACH
4512V/B/C
Macrocells 32 64 128 256 384 512
I/O + Dedicated Inputs 30+2/32+4 30+2/32+4/
64+10
64+10/92+4/
96+4
64+10/96+14/
128+4/160+4
128+4/192+4 128+4/208+4
t
PD
(ns) 2.52.52.73.03.53.5
t
S
(ns) 1.81.81.82.02.02.0
t
CO
(ns) 2.22.22.72.72.72.7
f
MAX
(MHz) 400 400 333 322 322 322
Supply Voltages (V) 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V
Pins/Package 44 TQFP
48 TQFP
44 TQFP
48 TQFP
100 TQFP 100 TQFP
128 TQFP
144 TQFP
1
100 TQFP
144 TQFP
1
176 TQFP
256 ftBGA
2
/
fpBGA
2, 3
176 TQFP
256 ftBGA/
fpBGA
3
176 TQFP
256 ftBGA/
fpBGA
3
1. 3.3V (4000V) only.
2. 128-I/O and 160-I/O configurations.
3. Use 256 ftBGA package for all new designs. Refer to PCN#14A-07 for 256 fpBGA package discontinuance.
