®
Includes
MAX 7000AE
Altera Corporation 1
MAX 7000A
Programmable Logic
Device
September 2003, ver. 4.5 Data Sheet
DS-M7000A-4.5
Features...
■ High-performance 3.3-V EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX
®
) architecture (see Table 1)
■ 3.3-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
– MAX 7000AE device in-system programmability (ISP) circuitry
compliant with IEEE Std. 1532
– EPM7128A and EPM7256A device ISP circuitry compatible with
IEEE Std. 1532
■ Built-in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1
■ Supports JEDEC Jam Standard Test and Programming Language
(STAPL) JESD-71
■ Enhanced ISP features
– Enhanced ISP algorithm for faster programming (excluding
EPM7128A and EPM7256A devices)
– ISP_Done bit to ensure complete programming (excluding
EPM7128A and EPM7256A devices)
– Pull-up resistor on I/O pins during in-system programming
■ Pin-compatible with the popular 5.0-V MAX 7000S devices
■ High-density PLDs ranging from 600 to 10,000 usable gates
■ Extended temperature range
f
For information on in-system programmable 5.0-V MAX 7000 or 2.5-V
MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family
Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet.
