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Altera Corporation 1
FLEX 6000
Programmable Logic
Device Family
March 2001, ver. 4.1 Data Sheet
A-DS-F6000-04.1
Features...
■ Provides an ideal low-cost, programmable alternative to high-
volume gate array applications and allows fast design changes
during prototyping or design testing
■ Product features
– Register-rich, look-up table- (LUT-) based architecture
– OptiFLEX
®
architecture that increases device area efficiency
– Typical gates ranging from 5,000 to 24,000 gates (see Table 1)
– Built-in low-skew clock distribution tree
– 100% functional testing of all devices; test vectors or scan chains
are not required
■ System-level features
– In-circuit reconfigurability (ICR) via external configuration
device or intelligent controller
– 5.0-V devices are fully compliant with peripheral component
interconnect Special Interest Group (PCI SIG) PCI Local Bus
Specification, Revision 2.2
– Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic
–MultiVolt
TM
I/O interface operation, allowing a device to bridge
between systems operating at different voltages
– Low power consumption (typical specification less than 0.5 mA
in standby mode)
– 3.3-V devices support hot-socketing
Note:
(1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 14,000 gates in addition to the listed typical gates.
Table 1. FLEX 6000 Device Features
Feature EPF6010A EPF6016 EPF6016A EPF6024A
Typical gates (1) 10,000 16,000 16,000 24,000
Logic elements (LEs) 880 1,320 1,320 1,960
Maximum I/O pins 102 204 171 218
Supply voltage (V
CCINT
) 3.3 V 5.0 V 3.3 V 3.3 V
