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TMS320C6743
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SPRS565B–APRIL 2009–REVISED JUNE 2011
TMS320C6743 Fixed/Floating-Point Digital Signal Processor
Check for Samples: TMS320C6743
1 TMS320C6743 Fixed/Floating-Point Digital Signal Processor
1.1 Features
12
Cycle
• Highlights
– Two Multiply Functional Units
– Up to 375-MHz FIxed/Floating-Point VLIW
DSP Core • Mixed-Precision IEEE Floating Point
Multiply Supported up to:
– Enhanced Direct-Memory-Access Controller
(EDMA3) – 2 SP x SP -> SP Per Clock
– Two External Memory Interfaces – 2 SP x SP -> DP Every Two Clocks
– Two Configurable 16550 type UART Modules – 2 SP x DP -> DP Every Three Clocks
– One Serial Peripheral Interface (SPI) – 2 DP x DP -> DP Every Four Clocks
– Multimedia Card (MMC)/Secure Digital (SD) • Fixed Point Multiply Supports Two 32 x
32-Bit Multiplies, Four 16 x 16-Bit
– Two Master/Slave Inter-Integrated Circuit
Multiplies, or Eight 8 x 8-Bit Multiplies per
Modules (I2C)
Clock Cycle, and Complex Multiples
– RMII Ethernet Media Access COntroller
– Instruction Packing Reduces Code Size
(EMAC)
– All Instructions Conditional
– Three Event Capture (eCAP) Modules
– Hardware Support for Modulo Loop
– Two Quadrature Encoding (eQEP) Modules
Operation
– Two Multi-Channel Audio Serial Ports
– Protected Mode Operation
(McASP)
– Exceptions Support for Error Detection and
– Programmable Real-Time Unit Subsystem
Program Redirection
(PRUSS)
• C674x Instruction Set Features
– Two 64-bit Timers (each configurable as
32-bit) – Superset of the C67x+™ and C64x+™ ISAs
• Applications – 3000/2250 C674x MIPS/MFLOPS
– Industrial Control – Byte-Addressable (8-/16-/32-/64-Bit Data)
– Networking – 8-Bit Overflow Protection
– High-Speed Encoding – Bit-Field Extract, Set, Clear
– Professional Audio™ – Normalization, Saturation, Bit-Counting
• Software Support – Compact 16-Bit Instructions
– TI DSP/BIOS™ • C674x Two Level Cache Memory Architecture
– Chip Support Library and DSP Library – 32K-Byte L1P Program RAM/Cache
• TMS320C674x Floating Point VLIW DSP Core – 32K-Byte L1D Data RAM/Cache
– Load-Store Architecture With Non-Aligned – 128K-Byte L2 Unified Mapped RAM/Cache
Support
– Flexible RAM/Cache Partition (L1 and L2)
– 64 General-Purpose Registers (32 Bit)
• Enhanced Direct-Memory-Access Controller 3
– Six ALU (32-/40-Bit) Functional Units (EDMA3):
• Supports 32-Bit Integer, SP (IEEE Single – 2 Transfer Controllers
Precision/32-Bit) and DP (IEEE Double
– 32 Independent DMA Channels
Precision/64-Bit) Floating Point
– 8 Quick DMA Channels
• Supports up to Four SP Additions Per
– Programmable Transfer Burst Size
Clock, Four DP Additions Every 2 Clocks
• 3.3V LVCMOS IOs
• Supports up to Two Floating Point (SP or
• Two External Memory Interfaces:
DP) Reciprocal Approximation (RCPxP)
– EMIFA
and Square-Root Reciprocal
• NOR (8-Bit-Wide Data)
Approximation (RSQRxP) Operations Per
1
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Instruments standard warranty. Production processing does not
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