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OMAP-L138
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SPRS586D–JUNE 2009– REVISED OCTOBER 2011
OMAP-L138 C6-Integra™ DSP+ARM® Processor
Check for Samples: OMAP-L138
1 OMAP-L138 C6-Integra™ DSP+ARM® Processor
1.1 Features
12
– Bit-Field Extract, Set, Clear
• Highlights
– Normalization, Saturation, Bit-Counting
– Dual Core SoC
– Compact 16-Bit Instructions
• 375/456-MHz ARM926EJ-S™ RISC MPU
• C674x Two Level Cache Memory Architecture
• 375/456-MHz C674x Fixed/Floating-Point
VLIW DSP – 32K-Byte L1P Program RAM/Cache
– Supports TI’s Basic Secure Boot – 32K-Byte L1D Data RAM/Cache
– Enhanced Direct-Memory-Access Controller – 256K-Byte L2 Unified Mapped RAM/Cache
(EDMA3)
– Flexible RAM/Cache Partition (L1 and L2)
– Serial ATA (SATA) Controller
• Enhanced Direct-Memory-Access Controller 3
– DDR2/Mobile DDR Memory Controller (EDMA3):
– Two Multimedia Card (MMC)/Secure Digital – 2 Channel Controllers
(SD) Card Interface
– 3 Transfer Controllers
– LCD Controller
– 64 Independent DMA Channels
– Video Port Interface (VPIF)
– 16 Quick DMA Channels
– 10/100 Mb/s Ethernet MAC (EMAC)
– Programmable Transfer Burst Size
– Programmable Real-Time Unit Subsystem
• TMS320C674x Floating-Point VLIW DSP Core
– Three Configurable UART Modules
– Load-Store Architecture With Non-Aligned
– USB 1.1 OHCI (Host) With Integrated PHY Support
– USB 2.0 OTG Port With Integrated PHY – 64 General-Purpose Registers (32 Bit)
– One Multichannel Audio Serial Port – Six ALU (32-/40-Bit) Functional Units
– Two Multichannel Buffered Serial Ports • Supports 32-Bit Integer, SP (IEEE Single
Precision/32-Bit) and DP (IEEE Double
• Dual Core SoC
Precision/64-Bit) Floating Point
– 375/456-MHz ARM926EJ-S™ RISC MPU
• Supports up to Four SP Additions Per
– 375/456-MHz C674x Fixed/Floating-Point
Clock, Four DP Additions Every 2 Clocks
VLIW DSP
• Supports up to Two Floating Point (SP or
• ARM926EJ-S Core
DP) Reciprocal Approximation (RCPxP)
– 32-Bit and 16-Bit (Thumb®) Instructions
and Square-Root Reciprocal
– DSP Instruction Extensions
Approximation (RSQRxP) Operations Per
– Single Cycle MAC
Cycle
– ARM® Jazelle® Technology
– Two Multiply Functional Units
– EmbeddedICE-RT™ for Real-Time Debug
• Mixed-Precision IEEE Floating Point
• ARM9 Memory Architecture
Multiply Supported up to:
– 16K-Byte Instruction Cache
– 2 SP x SP → SP Per Clock
– 16K-Byte Data Cache
– 2 SP x SP → DP Every Two Clocks
– 8K-Byte RAM (Vector Table)
– 2 SP x DP → DP Every Three Clocks
– 64K-Byte ROM
– 2 DP x DP → DP Every Four Clocks
• C674x™ Instruction Set Features
• Fixed Point Multiply Supports Two 32 x
32-Bit Multiplies, Four 16 x 16-Bit
– Superset of the C67x+™ and C64x+™ ISAs
Multiplies, or Eight 8 x 8-Bit Multiplies per
– Up to 3648/2746 C674x MIPS/MFLOPS
Clock Cycle, and Complex Multiples
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– Instruction Packing Reduces Code Size
– 8-Bit Overflow Protection
– All Instructions Conditional
1
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