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April 2016 Technical Note TN1279
www.latticesemi.com 1 TN1279_1.8
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Introduction
The MachXO3™ is an SRAM-based Programmable Logic Device that includes an internal Non-Volatile Configura-
tion Memory (NVCM) in the MachXO3L version and On-Chip Flash in the MachXO3LF version. This allows the
MachXO3L family to support the best of both worlds – infinitely configurable (SRAM) and non-volatile
(NVCM/Flash) capabilities. The MachXO3L/LF provides a rich set of features for programming and configuration of
the FPGA. You have many options available to you for building the programming solution that fits your needs. Each
of the options available will be described in detail so that you can put together the programming and configuration
solution that meets your needs.
MachXO3L/LF devices contain two types of memory, SRAM and NVCM (MachXO3L) or Flash (MachXO3LF).
SRAM memory contains the active configuration, essentially the “fuses” that define the behavior of the FPGA. The
active configuration is, in most cases, retrieved from a non-volatile memory. The non-volatile memory holds the
configuration data that is loaded into the FPGAs SRAM. The MachXO3L/LF provides an internal NVCM or Flash
memory that stores the configuration data loaded into the MachXO3L/LF SRAM.
MachXO3L/LF Features
Key programming and configuration features of MachXO3L devices are:
• Instant-on configuration from internal NVCM (MachXO3L) or Flash (MachXO3LF) – powers up in milliseconds
• Infinite number of configuration cycle through volatile SRAM technology
• MachXO3L multi-time (up to two times) programmability through non-volatile technology (NVCM)
• Single-chip, secure solution
• Multiple programming and configuration interfaces:
— 1149.1 JTAG
— Self download
— Slave SPI
— Master SPI
— Dual Boot
— I
2
C
• Programming and configuration ports:
— Slave SPI
— Master SPI
— I
2
C
— JTAG
• (MachXO3LF) User Flash Memory (UFM) for non-volatile data storage:
— Configuration Flash memory overflow
— EBR Initialization data
— Application specific data
• (MachXO3LF) Transparent programming of non-volatile memory
• Optional dual boot with external SPI memory
• Optional security bits for design protection
• Optional Bitstream Compression support
• TransFR Capability
— Leave alone I/O using Non-JTAG implementation
• SED support
MachXO3 Programming and
Configuration Usage Guide
