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Feature Summary
• 32-bit load/store RISC architecture
• Up to 15 general-purpose 32-bit registers
• 32-bit Stack Pointer, Program Counter, and Link Register reside in register file
• Fully orthogonal instruction set
• Pipelined architecture allows one instruction per clock cycle for most instructions
• Byte, half-word, word and double word memory access
• Fast interrupts and multiple interrupt priority levels
• Optional branch prediction for minimum delay branches
• Privileged and unprivileged modes enabling efficient and secure Operating Systems
• Innovative instruction set together with variable instruction length ensuring industry
leading code density
• Optional DSP extention with saturated arithmetic, and a wide variety of multiply
instructions
• Optional extensions for Java, SIMD, Read-Modify-Write to memory, and Coprocessors
• Architectural support for efficient On-Chip Debug solutions
• Optional MPU or MMU allows for advanced operating systems
• FlashVault™ support through Secure State for executing trusted code alongside
nontrusted code on the same CPU
32000D–04/2011
AVR32
Architecture
Document
