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8-Bit, High Bandwidth
Multiplying DAC with Serial Interface
Data Sheet
AD5425
Rev. D Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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FEATURES
2.5 V to 5.5 V supply operation
50 MHz serial interface
2.47 MSPS update rate
INL of ±0.25 LSB
10 MHz multiplying bandwidth
±10 V reference input
Low glitch energy: <2 nV-s
Extended temperature range: −40°C to +125°C
10-lead MSOP package
Guaranteed monotonic
4-quadrant multiplication
Power-on reset with brownout detection
LDAC
function
0.4 µA typical power consumption
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
GENERAL DESCRIPTION
The AD5425
1
is a CMOS, 8-bit, current output digital-to-analog
converter (DAC) that operates from a 2.5 V to 5.5 V power supply,
making it suitable for battery-powered applications and many
other applications.
This DAC utilizes a double buffered, 3-wire serial interface that
is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP
interface standards. An
LDAC
pin is also provided, which
allows simultaneous updates in a multiDAC configuration. On
power-up, the internal shift register and latches are filled with
0s and the DAC outputs are 0 V.
As a result of manufacturing on a CMOS submicron process,
this DAC offers excellent 4-quadrant multiplication charac-
teristics with large signal multiplying bandwidths of 10 MHz.
The applied external reference input voltage (V
REF
) determines
the full-scale output current. An integrated feedback resistor,
R
FB
, provides temperature tracking and full-scale voltage output
when combined with an external I to V precision amplifier.
The AD5425 is available in a small, 10-lead MSOP package.
FUNCTIONAL BLOCK DIAGRAM
SCLK
SYNC
AD5425
V
REF
I
OUT
2
I
OUT
1
R
FB
R
8-BIT
R-2R DAC
DAC REGISTER
SDIN
V
DD
GND
POWER-ON
RESET
LDAC
CONTROL LOGIC AND
INPUT SHIFT REGISTER
INPUT LATCH
03161-001
Figure 1.
1
U.S. Patent No. 5,969,657.
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