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66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
66AK2E0x Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
1 66AK2E0x Features and Description
1.1 Features
1
Interface, and SSL/TLS Security
• ARM
®
Cortex
®
-A15 MPCore™ CorePac
• ECB, CBC, CTR, F8, A5/3, CCM, GCM,
– Up to Four ARM Cortex-A15 Processor Cores at
HMAC, CMAC, GMAC, AES, DES, 3DES,
up to 1.4-GHz
Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
– 4MB L2 Cache Memory Shared by all Cortex-
Hash), MD5
A15 Processor Cores
• Up to 6.4 Gbps IPSec and 3 Gbps Air
– Full Implementation of ARMv7-A Architecture
Ciphering
Instruction Set
– Ethernet Subsystem
– 32KB L1 Instruction and Data Caches per Core
• Eight SGMII Ports with Wire Rate Switching
– AMBA 4.0 AXI Coherency Extension (ACE)
• IEEE1588 v2 (with Annex D/E/F) Support
Master Port, Connected to MSMC (Multicore
Shared Memory Controller) for Low Latency
• 8 Gbps Total Ingress/Egress Ethernet BW
Access to SRAM and DDR3
from Core
• One TMS320C66x DSP Core Subsystem (C66x
• Audio/Video Bridging (802.1Qav/D6.0)
CorePacs), Each With
• QOS Capability
– 1.4 GHz C66x Fixed/Floating-Point DSP Core
• DSCP Priority Mapping
• 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
• Peripherals
• 19.2 GFlops/Core for Floating Point @
– Two PCIe Gen2 Controllers with Support for
1.2 GHz
• Two Lanes per Controller
– Memory
• Supports Up to 5 GBaud
• 32K Byte L1P Per CorePac
– One HyperLink
• 32K Byte L1D Per CorePac
• Supports Connections to Other KeyStone
• 512K Byte Local L2 Per CorePac
Architecture Devices Providing Resource
• Multicore Shared Memory Controller (MSMC)
Scalability
– 2 MB SRAM Memory Shared by DSP CorePacs
• Supports Up to 50 GBaud
and ARM CorePac
– 10-Gigabit Ethernet (10-GbE) Switch Subsystem
– Memory Protection Unit for Both SRAM and
• Two SGMII/XFI Ports with Wire Rate
DDR3_EMIF
Switching and MACSEC Support
• Multicore Navigator
• IEEE1588 v2 (with Annex D/E/F) Support
– 8k Multi-Purpose Hardware Queues with Queue
– One 72-Bit DDR3/DDR3L Interface with Speeds
Manager
Up to 1600 MTPS in DDR3 Mode
– One Packet-Based DMA Engine for Zero-
– EMIF16 Interface
Overhead Transfers
– Two USB 2.0/3.0 Controllers
• Network Coprocessor
– USIM Interface
– Packet Accelerator Enables Support for
– Two UART Interfaces
• Transport Plane IPsec, GTP-U, SCTP,
– Three I
2
C Interfaces
PDCP
– 32 GPIO Pins
• L2 User Plane PDCP (RoHC, Air Ciphering)
– Three SPI Interfaces
• 1 Gbps Wire Speed Throughput at 1.5
– One TSIP
MPackets Per Second
• Support 1024 DS0s
– Security Accelerator Engine Enables Support for
• Support 2 Lanes at 32.768/16.3848.192
• IPSec, SRTP, 3GPP and WiMAX Air
Mbps Per Lane
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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