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September 2013 Doc ID 022384 Rev 2 1/49
AN3995
Application note
Getting started tutorial
for SPC564Bxx and SPC56ECxx family
Introduction
The SPC564Bxx and SPC56ECxx is a family of Power Architecture
®
based microcontrollers
that target automotive vehicle body and gateway applications such as Central body
controller, Smart junction boxes, Front modules, High end gateway, Combined Body
controller and gateway.
These dual core architecture devices contain an e200z4d and e200z0h core, compliant with
the Power Architecture standard.
It provides the scalability needed to implement platform approaches and delivers the
performance required by increasingly sophisticated software architectures.
These devices feature up to 3 MB of internal Flash and up to 256 KB of internal SRAM
memory.
It operates at speeds of up to 120 MHz and offers high performance processing optimized
for low power consumption.
The SPC564Bxx and SPC56ECxx family expands the range of the SPC560B/C
microcontroller family but differs from it by being the first device to feature the e200z4d core
and the e200z0h in a dual core configuration.
The differences between this family and the previous one (SPC560B/C) mean that the
initialization and configuration are different.
This application note details the steps required to properly initialize the SPC564Bxx and
SPC56ECxx from reset as well as how to control the second core. An example code is
described throughout the application note to explain the steps.
It is intended that this application note is read along with the SPC564Bxx and SPC56ECxx
Reference Manual, RM0070 that can be obtained from the STMicroelectronics
®
website at
http://www.st.com (see Section C.1: Reference document).
www.st.com
