下载
Haptics Enabled CapSense
®
Controller
CY8C20336H, CY8C20446H
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 •408-943-2600
Document Number: 001-56223 Rev. *E Revised November 27, 2012
Features
■ 1.71-V to 5.5-V operating range
■ Low power CapSense
®
block
❐ Configurable capacitive sensing elements
❐ Supports combination of CapSense buttons, sliders,
touchpads, touchscreens, and proximity sensors
■ Powerful Harvard-architecture processor
❐ M8C CPU speed can be up to 24 MHz or sourced by an
external crystal, resonator, or clock signal
❐ Low power at high speed
❐ Interrupt controller
❐ Temperature range: –40 °C to +85 °C
■ Flexible on-chip memory
❐ Two program/data storage size options:
• CY8C20336H: 8 KB flash / 1 KB SRAM
• CY8C20446H: 16 KB flash / 2 KB SRAM
❐ 50,000 flash erase/write cycles
❐ Partial flash updates
❐ Flexible protection modes
❐ In-System Serial Programming (ISSP)
■ Precision, programmable clocking
❐ Internal main oscillator (IMO): 6/12/24 MHz ± 5%
❐ Internal low-speed oscillator (ILO) at 32 kHz for watchdog
and sleep timers
❐ Precision 32-kHz oscillator for optional external crystal
■ Programmable pin configurations
❐ Up to 28 general-purpose I/Os (GPIOs) (depending on the
package)
❐ Dual-mode GPIO: All GPIOs support digital I/O and analog
inputs
❐ 25-mA sink current on each GPIO
• 120-mA total sink current on all GPIOs
❐ Pull-up, high Z, open drain modes on all GPIOs
❐ CMOS drive mode: 5-mA source current on ports 0 and 1
and 1 mA on ports 2, 3, and 4
• 20-mA total source current on all GPIOs
❐ Selectable, regulated digital I/O on port 1
❐ Configurable input threshold on port 1
❐ Hot swap capability on all port 1 GPIOs
■ Integrates Immersion TS2000 Haptics technology for ERM
drive control
■ Versatile analog mux
❐ Common internal analog bus
❐ Simultaneous connection of I/O
❐ High Power supply rejection ratio (PSRR) comparator
❐ Low dropout voltage regulator for all analog resources
■ Additional system resources
❐ I2C slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• No clock stretching (under most conditions)
• Implementation during sleep modes with less than 100 µA
• Hardware address validation
❐ SPI master and slave: Configurable 46.9 kHz to 12 MHz
❐ Three 16-bit timers
❐ Watchdog and sleep timers
❐ Internal voltage reference
❐ Integrated supervisory circuit
❐ 8- to 10-bit incremental analog-to-digital converter (ADC)
❐ Two general-purpose high-speed, low-power analog
comparators
■ Complete development tools
❐ Free development tool (PSoC Designer™)
❐ Full featured, In-Circuit Emulator (ICE) and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
■ Package options
❐ CY8C20336H:
• 24-pin 4 × 4 × 0.6 mm QFN
❐ CY8C20446H:
• 32-pin 5 × 5 × 0.6 mm QFN
页面指南
