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Data sheet acquired from Harris Semiconductor
SCHS147I
Features
• Select One Of Eight Data Outputs
Active Low for 138, Active High for 238
• l/O Port or Memory Selector
• Three Enable Inputs to Simplify Cascading
• Typical Propagation Delay of 13 ns at V
CC
= 5 V,
C
L
= 15 pF, T
A
= 25
o
C
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2 V to 6 V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5 V
• HCT Types
- 4.5-V to 5.5-V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8 V (Max), V
IH
= 2 V (Min)
- CMOS Input Compatibility, I
l
≤ 1µA at V
OL
, V
OH
Description
The ’HC138, ’HC238, ’HCT138, and ’HCT238 are high-speed
silicon-gate CMOS decoders well suited to memory address
decoding or data-routing applications. Both circuits feature
low power consumption usually associated with CMOS
circuitry, yet have speeds comparable to low-power Schottky
TTL logic. Both circuits have three binary select inputs (A0,
A1, and A2). If the device is enabled, these inputs determine
which one of the eight normally high outputs of the
HC/HCT138 series go low or which of the normally low
outputs of the HC/HCT238 series go high.
Two active low and one active high enables (
E1, E2, and E3)
are provided to ease the cascading of decoders. The
decoder’s eight outputs can drive ten low-power Schottky
TTL equivalent loads.
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C) PACKAGE
CD54HC138F3A -55 to 125 16 Ld CERDIP
CD54HC238F3A -55 to 125 16 Ld CERDIP
CD54HCT138F3A -55 to 125 16 Ld CERDIP
CD54HCT238F3A -55 to 125 16 Ld CERDIP
CD74HC138E -55 to 125 16 Ld PDIP
CD74HC138M -55 to 125 16 Ld SOIC
CD74HC138MT -55 to 125 16 Ld SOIC
CD74HC138M96 -55 to 125 16 Ld SOIC
CD74HC238E -55 to 125 16 Ld PDIP
CD74HC238M -55 to 125 16 Ld SOIC
CD74HC238MT -55 to 125 16 Ld SOIC
CD74HC238M96 -55 to 125 16 Ld SOIC
CD74HC238NSR -55 to 125 16 Ld SOP
CD74HC238PW -55 to 125 16 Ld TSSOP
CD74HC238PWR -55 to 125 16 Ld TSSOP
CD74HC238PWT -55 to 125 16 Ld TSSOP
CD74HCT138E -55 to 125 16 Ld PDIP
CD74HCT138M -55 to 125 16 Ld SOIC
CD74HCT138MT -55 to 125 16 Ld SOIC
CD74HCT138M96 -55 to 125 16 Ld SOIC
CD74HCT238E -55 to 125 16 Ld PDIP
CD74HCT238M -55 to 125 16 Ld SOIC
CD74HCT238M96 -55 to 125 16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
October 1997 - Revised August 2004
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2004, Texas Instruments Incorporated
CD54/74HC138, CD54/74HCT138,
CD54/74HC238, CD54/74HCT238
High-Speed CMOS Logic 3- to 8-Line Decoder/
Demultiplexer Inverting and Noninverting
[ /Title
(CD74
HC138
,
C
D74
HCT13
8,
CD74
HC238
,
C
D74
HCT23
8)
/Sub-
ject
(High
Speed
